The present invention relates to a semiconductor memory apparatus, and more particularly, to a data input device of a semiconductor memory apparatus which buffers inputted data and a method for controlling the same.
Semiconductor memory apparatuses have been essential components in most electronic products. For example, semiconductor memory apparatuses are used in various electronic products such as personal computers, televisions, audio sets and communication terminals. The semiconductor memory apparatuses used in various fields receive and store data from different electronic elements or appliances, and provide the stored data to different electronic elements or appliances upon request. Accordingly, the semiconductor memory apparatuses need circuits or devices associated with the input and output of data between the different electronic elements or appliances and the semiconductor memory apparatuses. That is to say, the semiconductor memory apparatuses need circuits or devices for transmitting and receiving data to and from the different electronic elements or appliances.
In order to store data in a semiconductor memory apparatus, an input buffer is used to temporarily store data received from a different electronic element or appliance. Such an input buffer functions to receive data from the external electronic element or appliance, amplify the received data and convert the amplified data to a level (CMOS level) to be processed in the semiconductor memory apparatus.
This will be described with reference to FIG. 1.
FIG. 1 is a diagram illustrating a conventional circuit for generating a differential signal as an output in an input buffer of a semiconductor memory apparatus.
The circuit includes an NMOS transistor N3 which receives an input signal INPUT through the gate thereof and an NMOS transistor N2 which receives a reference signal VREF through the gate thereof. Also, the source terminals of the NMOS transistor N3 and the NMOS transistor N2 are connected with each other so that current flows through an NMOS transistor N1. An output signal RX_OUTB is outputted from the drain terminal of the NMOS transistor N3. The output signal RX_OUTB is then outputted through an inverter IV1 which is connected in series to the NMOS transistor N3.
PMOS transistors P1 and P2 are respectively connected in series to the drain terminals of the NMOS transistors N2 and N3. The PMOS transistors P1 and P2, which have the gate terminals connected with each other, constitute a current mirror type. The PMOS transistors P1 and P2 are supplied with an external supply voltage VDD through the respective source terminals thereof.
The NMOS transistor N1 implements a control function of enabling and disabling the operation of a differential amplifier which is configured as described above. That is to say, if the NMOS transistor N1 is turned on, as a current path is formed via the NMOS transistor N1 to a ground voltage VSS, the differential amplifier switches to a status in which it can operate. Conversely, if the NMOS transistor N1 is turned off, as the current path to the ground voltage VSS is shut off, the operation of the differential amplifier is interrupted. Accordingly, an enable signal ENABLE is inputted to the gate terminal of the NMOS transistor N1. The enable signal ENABLE is obtained from the output of a NOR gate NOR1 which NORs a clock enable bar signal CKEB and the ground signal VSS.
A conventional data input device of a semiconductor memory apparatus, which is configured as described above, compares the input signal INPUT and the reference signal VREF, and generates the output signal RX_OUTB corresponding to a differential signal between the two signals. The output signal RX_OUTB generated in this way and a signal OUT inverted by the inverter IV1 are outputted. Therefore, the conventional data input device of a semiconductor memory apparatus generates the output signal RX_OUTB corresponding to the differential signal between the input signal INPUT and the reference signal VREF and the desired output signal OUT obtained by inverting the output signal RX_OUTB.
In the conventional data input device of a semiconductor memory apparatus, when the enable signal ENABLE generated by a clock enable signal externally inputted is in a high state, if an external input is greater than the reference voltage VREF, a high signal is generated, and if the external input is less than the reference voltage VREF, a low signal is generated.
Conversely, in the conventional data input device of a semiconductor memory apparatus, when the enable signal ENABLE generated by the clock enable signal externally inputted is in a low state, since the NMOS transistor N1 is turned off and current flow is cut off, the data input device does not operate regardless of whether or not an input signal is externally applied.
FIG. 2 illustrates a scheme in which the enable signal is generated by a clock enable signal. Referring to FIG. 2, if a clock enable signal CKE is a high signal, since the enable signal ENABLE inputted to the data input device is converted to a high level, the data input device of a semiconductor memory apparatus consumes current.
FIG. 3 is a timing diagram illustrating the operation of the conventional data input device of a semiconductor memory apparatus in a standby state. Referring to FIG. 3, the clock enable signal CKE and an external command signal CSB are in a high state, and, while other external command signals RASB, CASB and WEB toggle per every other clock signal and an address A toggles once every four clock signals, current is consumed.
As a consequence, in the conventional data input device of a semiconductor memory apparatus, due to the fact that current consumption increases in the standby state, a standby IDD curve as shown in FIG. 4 is obtained. Specifically, a hump occurs in the IDD curve in performing a full charge-pumping operation immediately after power supply, and thereafter, the standby IDD curve linearly increases. Accordingly, in the conventional data input device of a semiconductor memory apparatus, controlling current consumption in the standby state is desirable.